Japanese Patent Application No. 2001-143635, filed on May 14, 2001, is hereby incorporated by reference in its entirety.
The present invention relates to a signal detection circuit, and a data transfer control device and electronic equipment using the same.
The universal serial bus (USB) standard has recently attracted attention as an interface standard for connections between personal computers and peripheral equipment (broadly speaking: electronic equipment). This USB standard has the advantage of enabling the use of connectors of the same standard to connect peripheral equipment such as a mouse, keyboard, and printer, which are connected by connectors of different standards in the prior art, and of making it possible to implement plug-and-play and hot-plug features.
In comparison with the IEEE 1394 standard, which is also attracting notice as a standard for the same serial bus interface, this USB standard has a problem in that the transfer speed thereof is slower.
Under such circumstances, the USB 2.0 standard was established and is attracting attention, USB 2.0 allowing a data transfer speed of 480 Mbps (High Speed (HS) mode) which is much faster than the speed achievable according to the USB 1.1 standard while maintaining backward compatibility with the USB 1.1 standard. USB 2.0 Transceiver Macrocell Interface (UTMI) was also established in which specifications for interfaces for physical layer circuits and logical layer circuits according to USB 2.0 were defined.
According to one aspect of the present invention, there is provided a signal detection circuit which detects an input signal, comprising:
a peak hold circuit which holds a peak value of the input signal at a given node;
a constant potential setting circuit which returns a potential at the node to a given constant potential; and
a comparison circuit which compares the potential at the node with a given reference level,
wherein the signal detection circuit detects the input signal based on a comparison result by the comparison circuit.
According to another aspect of the present invention, there is also provided a signal detection circuit which detects a differential pair of input signals, comprising:
a differential amplifier which outputs a differential pair of output signals which are amplified based on the differential pair of input signals;
first and second peak hold circuits which hold peak values of the differential pair of output signals at a given node;
a constant potential setting circuit which returns the potential at the node to a given constant potential such that the potential changes slower than a potential change caused by holding the peak values; and
a comparison circuit which compares the potential at the node with a given reference level,
wherein the signal detection circuit detects the input signals based on a comparison result by the comparison circuit.